("Work" home page
for Thomas R. Arneberg)

NEWS FLASH: in April 2006, I left SGI, and went to Cray, Inc. (I went "back" to Cray even though I never left!) My new Cray page will be here.

Welcome to my SGI home page. I have been a design engineer at Cray/SGI in Chippewa Falls since 1991. (Before that, I worked at Bipolar Integrated Technology, a startup in Beaverton, Oregon; preceded by three years at Honeywell Digital Product Center in Colorado Springs; preceded by Sperry Univac Semiconductor Division in Eagan, Minnesota.)

I was the manager of the IC Design group for the CRAY SV1 system, named "Supercomputer Product of the Year" in late 1999 by Scientific Computing and Automation magazine.

In April 2000, I switched over to lead the static timing effort (using IBM's Einstimer) and help forge a new ASIC design methodology on another project, now known as the Altix (see below). (Shortly after that simple project transfer, SGI decided to sell the vector machine business to Tera Computer of Seattle, which subsequently renamed their company Cray, Inc. But about 2/3 of the original Cray Research people in Chippewa Falls, including me, are still with SGI, designing ever bigger and better scalable supercomputers, albeit non-vector ones.)

Obviously, there's not much I can put about our current computer and chip designs on a public home page. If you are inside the SGI firewall, you can see most of what I'm doing on this page.

For those outside our firewall, here are some public links:

January 2003: SGI announces the Altix!

For three years, our ASIC physical design group here in Chippewa Falls worked to help design the Shub chip ("Scalable Hub"), which made possible the new Altix Linux Supercomputer. By all accounts, the Altix is the world's most powerful Linux system. I am not good at discerning what I can tell people about internal projects, but I guess it's okay to quote what I can already find on other public web pages, so here goes:

Shub was a huge chip, with 13 million gates and a 18 different clock domains, up to 800 MHz. The ASIC was designed with our own custom hierarchical design flow (see patent #6,684,373), with 43 different blocks of logic, some as big as 1.3 million gates.

It uses the IBM SA27e technology, a 0.18-micron process with six layers of metal and 1124 signal I/Os. More details:

This page is maintained by Tom Arneberg (
(Last modified: $Date: 2005/08/18 15:48:32 $)